A field-effect transistor (FET) is a type of transistor commonly used in Ultra Large Scale Integration (ULSI). In the FET, current flows along a semiconductor path called the channel. At one end of the channel, there is an electrode called the source. At the other end of the channel, there is an electrode called the drain. The physical dimensions of the channel are fixed, but its number of electrical carriers can be varied by the application of a voltage to a control electrode called the gate. The conductivity of the FET depends, at any given instant in time, on the number of electrical carriers of the channel. A small change in gate voltage can cause a large variation in the current from the source to the drain. This is how the FET amplifies signals. In one popular type of FET, known as a MOSFET, the channel can be either N-type or P-type semiconductor. The gate electrode is a piece of metal whose surface is insulated from the channel by a dielectric layer between the gate electrode and the channel and there is little current between the gate and the channel during any part of the signal cycle. This gives the MOSFET an extremely large input impedance.
One recent technique for improving the performance of field-effect transistors involves using dual-gates. In a dual-gated transistor, a top gate and a bottom gate are formed around an active region. Specifically, the advantages for dual gate devices over their single gate counterparts include: a higher transconductance and improved short-channel effects. As a result, higher device on-current is achieved for a given off-current.
Within a dual gate device, the bottom gate must be aligned with the top gate, as well as the source and drain junctions, in order to avoid highly penalizing parasitic capacitance. Furthermore, the top and bottom gates must be connected by a low resistance path having low parasitic capacitances with the other elements present (e.g., substrate, drain, etc.). This alignment has proven very difficult with conventional fabrication techniques and a structure known as FinFET has been proposed as showing promise as a dual-gated device.
A FinFET turns the silicon channel on its side thereby yielding access to a front gate and back gate from the top of the wafer during processing. This makes self-alignment of the source and drain regions and both gates relatively straightforward using conventional lithographic techniques. In a FinFET, the width of the device is determined by the height of the fin.
When fabricating a FinFET using sidewall imaging transfer techniques, the spacer used to define the gate dimension wraps up and down the fin sidewalls. While a taller fin provides a device with more performance, it also results in a longer vertical distance over which the spacer runs. Thus, when etching the gate conductor material along the spacer's edges, the gate conductor must be etched down the entire height of the fin while maintaining a straight vertical profile and while not punching through other layers like the mask, or a protective cap. As a result, as the fins of FinFETs reach larger heights, techniques are needed that allow fabricating gate structures without requiring very long directional etching when forming dimension-critical features of the FinFET such as channel or gate length.